The present invention relates to a semiconductor device, and more specifically to a method of increasing the level of integration while maintaining the reliability of a device by using a stacked structure.
A semiconductor device comprises of a plurality of circuits. Generally, a memory semiconductor device like DRAM is comprised of a cell region, a core region, and a peripheral region. The cell region stores data. The core region has a circuit for accessing data stored in the cell region. The peripheral region has a circuit for driving the memory semiconductor device and the data input/output.
In the cell region, memory cells including a cell transistor and a cell capacitor are arranged in an array type. Such a cell region includes a plurality of unit cell arrays.
In the core region, the circuit including a sub-word line driver and a sense amplifier is formed. At this time, the sub-word line driver drives the sub-word line according to the voltage level of the main word line. The sense amplifier senses and amplifies the data of a cell.
A bank includes a plurality of unit cell arrays and a plurality of core regions. For example, in the case of the DDR2 512 Mbit device, it has four banks. The peripheral region in which the circuit including a free decoder, an input buffer, and an output buffer is formed is provided between these banks.
Recently, more circuits, particularly, more memory cells have to be formed in a limited chip area, since high integration is required as the size of the semiconductor device has been reduced.
However, a trade-off relation exists between the net die increment and the reliability assurance of a device. Thus, the reliability of a device is decreased if the net die is increased. That is, in the current DRAM structure, there is a structural limit in increasing the net die while not reducing the reliability of a device.